View SC624_2033978.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

power management 1 SC624 led light management unit charge pump, 4 leds, dual ldos, and semwire tm interface ? 2007 semtech corporation features input supply voltage range 3.0v to 5.5v charge pump modes 1x, 1.5x and 2x four programmable current sinks with 32 steps from 0.5ma to 25ma two user-con gurable 100ma low-noise ldo regulators charge pump frequency 250khz semwire tm single wire interface up to 75kbit/s backlight current accuracy 1.5% typical backlight current matching 0.5% typical programmable fade-in/fade-out for main backlight automatic sleep mode (leds o ) i q = 100a low shutdown current 0.1a (typical) ultra-thin package 3mm x 3mm x 0.6mm fully weee and rohs compliant applications cellular phone backlighting pda backlighting camera i/o and core power ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC624 is a high e ciency charge pump led driver using semtechs proprietary mahxlife tm technology. performance is optimized for use in single-cell li-ion battery applications. the charge pump provides backlight current in conjunction with four matched current sinks. the load and supply conditions determine whether the charge pump operates in 1x, 1.5x, or 2x mode. an optional fading feature that gradually adjusts the backlight current is provided to simplify control software. the SC624 also provides two low-dropout, low-noise linear regulators for powering a camera module or other peripheral circuits. the SC624 uses the proprietary semwire tm single wire interface. the interface controls all functions of the device, including backlight current and two ldo voltage outputs. the single wire implementation minimizes microcontroller and interface pin counts. in sleep mode, the device reduces quiescent current to 100 a while continuing to monitor the serial interface. the two ldos can be enabled when the device is in sleep mode. total current reduces to 0.1 a in shutdown. SC624 vin swif byp agnd pgnd vout bl1 c in 1 f main backlight ldo1 gref c1+ semwire interface v ldo1 = 2.5v to 3.3v v ldo2 = 1.5v to 1.8v v bat c byp 22nf c out 2.2 f c ldo2 1 f c ldo1 1 f c2 1 f c1 1 f ldo2 bl2 bl3 bl4 c2+ c1- c2- us patents: 6,504,422; 6,794,926 typical application circuit june 27, 2007
SC624 2 pin con guration marking information ordering information device package SC624ultrt (1)(2) mlpq-ut-20 33 SC624evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) available in lead-free package only. device is weee and rohs compliant. top view 1 2 3 4 t c2- bl1 pgnd nc 5 678910 gref swif ldo2 nc byp ldo1 15 14 13 12 11 16 17 18 19 20 bl2 nc agnd bl4 bl3 vout vin c1- c2+ c1+ yyww = date code xxxx = semtech lot no. 624 yyww xxxx mlpq-ut-20; 3x3, 20 lead ja = 35c/w
SC624 3 exceeding the above speci cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114-b. (2) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with thermal vias under the exposed pad per je sd51 standards. absolute maximum ratings vin (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 vout (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 c1+, c2+ (v) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v out + 0.3) pin voltage all other pins (v) . . . . . . . . . -0.3 to (v in + 0.3) vout short circuit duration . . . . . . . . . . . . . . . . con tinuous vldo1, vldo2 short circuit duration . . . . . . . con tinuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions ambient temperature range (c) . . . . . . . . -40 < t a < +85 vin (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 < v in < 5.5 vout (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 < v out < 5.25 voltage di erence between any two leds (v) . . . . . . < 1.2 thermal information thermal resistance, junction to ambient (2) (c/w) . . . . 35 maximum junction temperature (c) . . . . . . . . . . . . . . +150 storage temperature range (c) . . . . . . . . . . . . -65 to +150 peak ir reflow temperature (10s to 30s) (c) . . . . . . . +260 unless otherwise noted, t a = +25c for typ, -40oc to +85c for min and max, t j(max) = 125oc, v in = 3.0v to 4.2v, c in = c 1 = c 2 = 2.2f, c out = 4.7f (esr = 0.03), v f 1.2v (1) parameter symbol conditions min typ max units supply speci cations shutdown current i q(off) shutdown, v in = 4.2v 0.1 2 a total quiescent current i q sleep (ldos o ), swif = v in 100 160 a sleep (ldos on), swif = v in , v in > (v ldo + 300mv), i ldo < 200ma 220 340 charge pump in 1x mode, 4 backlights on 3.8 4.65 ma charge pump in 1.5x mode, 4 backlights on 4.6 5.85 charge pump in 2x mode, 4 backlights on 4.6 5.85 fault protection output short circuit current limit i out(sc) vout pin shorted to gnd 300 ma over-temperature t otp 160 c electrical characteristics
SC624 4 parameter symbol conditions min typ max units fault protection (continued) charge pump over-voltage protection v ovp vout pin open circuit, v out = v ovp rising threshold 5.3 5.7 6.0 v undervoltage lockout v uvlo decreasing v in 2.4 v v uvlo-hys 300 mv charge pump electrical speci cations maximum total output current i out(max) v in > 3.4v, sum of all active led currents, v out(max) = 4.2v 100 ma backlight current setting i bl nominal setting for bl1 thru bl4 0.5 25 ma backlight current accuracy i bl_acc v in = 3.7v, i bl = 12ma, t a = 25c -8 1.5 +8 % backlight current matching i bl-bl v in = 3.7v, i bl = 12ma (2) -3.5 0.5 +3.5 % 1x mode to 1.5x mode falling transition voltage v trans1x i out = 40ma, i bln = 10ma, v out = 3.2v 3.27 v 1.5x mode to 1x mode hysteresis v hyst1x i out = 40ma, i bln = 10ma, v out = 3.2v 250 mv 1.5x mode to 2x mode falling transition voltage v trans1.5x i out = 40ma, i bln = 10ma, v out = 4.0v (3) 2.92 v 2x mode to 1.5x mode hysteresis v hyst1.5x i out = 40ma, i bln = 10ma, v out = 4.0v (3) 300 mv current sink o -state leakage current i bln v in = v bln = 4.2v 0.1 1 a pump frequency f pump v in = 3.2v 250 khz ldo electrical speci cations ldo1 voltage setting v ldo1 range of nominal settings in 100mv increments 2.5 3.3 v ldo2 voltage setting v ldo2 range of nominal settings in 100mv increments 1.5 1.8 v ldo1, ldo2 output voltage accuracy v ldo1, v ldo2 v in = 3.7v, i ldo = 1ma -3.5 3 +3.5 % line regulation v line ldo1, i ldo1 = 1ma, v out = 2.8v 2.1 7.2 mv ldo2, i ldo2 = 1ma, v out = 1.8v 1.3 4.8 electrical characteristics (continued)
SC624 5 electrical characteristics (continued) parameter symbol conditions min typ max units ldo electrical speci cations (continued) load regulation v load v ldo1 = 3.3v, v in = 3.7v, i ldo1 = 1ma to 100 ma 25 mv v ldo2 = 1.8v, v in = 3.7v, i ldo2 = 1ma to 100 ma 20 dropout voltage (4) v d i ldo1 = 100ma 100 150 mv current limit i lim 200 ma power supply rejection ratio psrr ldo1 2.5v < v ldo1 < 3v, f < 1khz, c byp = 22nf, i ldo1 = 50ma, v in = 3.7v with 0.5v p-p ripple 50 db psrr ldo2 f < 1khz, c byp = 22nf, i ldo2 = 50ma, v in = 3.7v with 0.5v p-p ripple 60 output voltage noise e n-ldo1 ldo1, 10hz < f < 100khz, c byp = 22nf, c ldo = 1f, i ldo1 = 50 ma, v in = 3.7v, 2.5v < v ldo1 < 3v 100 v rms e n-ldo2 ldo2, 10hz < f < 100khz, c byp = 22nf, c ldo = 1f, i ldo2 = 50 ma, v in = 3.7v 50 minimum output capacitor c ldo(min) 1f digital i/o electrical speci cations (swif) input high threshold v ih v in = 5.5v 1.6 v input low threshold v il v in = 3.0v 0.4 v input high current i ih v in = 5.5v -1 +1 a input low current i il v in = 5.5v -1 +1 a semwire bit rate f swif 10 75 kbit/s semwire start-up time (5) t en 1ms semwire disable time (6) t dis 10 ms semwire data latch delay (7) d dl 5 bit notes: (1) v f is the voltage difference between any two leds. (2) current matching equals [i bl(max) - i bl(min ] / [i bl(max) + i bl(min) ]. (3) test voltage is v out = 4.0v a relatively extreme led voltage to force a transition during test. typically v out = 3.2v for white leds. (4) dropout is de ned as (v in - v ldo1 ) when v ldo1 drops 100mv from nominal. dropout does not apply to ldo2 since it has a maximum output voltage of 1.8v. (5) the semwire start-up time is the minimum period that the swif pin must be held high to enable the part before commencing communication. (6) the semwire disable time is the minimum period that the swif pin must be pulled low to shut the part down. (7) the semwire data latch delay is the maximum duration after communication has ended before the register is updated.
SC624 6 typical characteristics battery current (4 leds) 25ma each 100 110 120 130 140 150 160 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) battery current (ma) v out =3.66v, i out =100ma, 25 c backlight e ciency (4 leds) 25ma each 50 60 70 80 90 100 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) % efficiency v out =3.66v, i out =100ma, 25 c backlight e ciency (4 leds) 12ma each v out =3.50v, i out =48ma, 25c 50 60 70 80 90 100 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) % efficiency backlight e ciency (4 leds) 5.0ma each 50 60 70 80 90 100 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) % efficiency v out =3.33v, i out =20ma, 25c battery current (4 leds) 5.0ma each 15 20 25 30 35 40 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) battery current (ma) v out =3.33v, i out =20ma, 25c battery current (4 leds) 12ma each 45 52 59 66 73 80 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) battery current (ma) v out =3.50v, i out =48ma, 25c
SC624 7 typical characteristics (continued) psrr vs. frequency (ldo2) -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) psrr (db) v in =3.7v at 25c, i ldo2 =50ma, v ldo2 =1.8v psrr vs. frequency (ldo1) -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) psrr (db) v in =3.7v at 25c, i ldo1 =50ma, v ldo1 =2.8v load regulation (ldo1) -24 -16 -8 0 8 16 24 0306090 120 150 i ldo1 (ma) output voltage variation (mv) v ldo1 =3.3v, v in =3.7v, 25c load regulation (ldo2) -24 -16 -8 0 8 16 24 0 30 60 90 120 150 i ldo2 (ma) output voltage variation (mv) v ldo2 =1.8v, v in =3.7v, 25c
SC624 8 typical characteristics (continued) noise vs load current (ldo1) 50 60 70 80 90 100 0 20 40 60 80 100 i ldo1 (ma) noise ( v) v ldo1 =2.8v, v in =3.7v, 25c noise vs load current (ldo2) 0 20 40 60 80 100 0 20 40 60 80 100 i ldo2 (ma) noise ( v) v ldo2 =1.8v, v in =3.7v, 25c line regulation (ldo1) -3 -2 -1 0 1 2 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) output voltage variation (mv) v ldo1 =2.8v, i ldo1 =1ma, 25c line regulation (ldo2) -3 -2 -1 0 1 2 3.0 3.2 3.4 3.6 3.8 4.0 4.2 v in (v) output voltage variation (mv) v ldo2 =1.8v, i ldo2 =1ma, 25c
SC624 9 typical characteristics (continued) load transient response (ldo2) falling edge time (200 s/div) v ldo2 (50mv/div) i ldo2 (100ma/div) v in =3.7v, v ldo2 =1.8v, i ldo2 =100 to 1ma load transient response (ldo1) rising edge time (20 s/div) v ldo1 (50mv/div) i ldo1 (100ma/div) v in =3.7v, v ldo1 =2.8v, i ldo1 =1 to 100ma time (200 s/div) load transient response (ldo1) falling edge v in =3.7v, v ldo1 =2.8v, i ldo1 =100 to 1ma v ldo1 (50mv/div) i ldo1 (100ma/div) time (20 s/div) load transient response (ldo2) rising edge v in =3.7v, v ldo2 =1.8v, i ldo2 =1 to 100ma v ldo2 (50mv/div) i ldo2 (100ma/div) output short circuit current limit time (1ms/div) v out (1v/div) i out (100ma/div ) v out =0v, v in =4.2v, 25c output open circuit protection time (200 s/div) v bl1 (500mv/div) v out (2v/div) i bl1 (20ma/div ) v in =3.7v, 25c
SC624 10 pin descriptions pin # pin name pin function 1 c2- negative connection to bucket capacitor 2 requires a 1f capacitor connected to c2+ 2 pgnd ground pin for high current charge pump 3 nc unused pin do not terminate 4 bl1 current sink output for main backlight led 1 leave this pin open if unused 5 bl2 current sink output for main backlight led 2 leave this pin open if unused 6 bl3 current sink output for main backlight led 3 leave this pin open if unused 7 bl4 current sink output for main backlight led 4 leave this pin open if unused 8 agnd analog ground pin connect to ground and separate from pgnd current 9 gref ground reference connect to ground 10 nc unused pin do not terminate 11 swif semwire single wire interface pin used to enable/disable the device and to set up all internal registers (refer to register map and semwire interface sections) 12 nc unused pin do not terminate 13 byp bypass pin for voltage reference connect with a 22nf capacitor to agnd 14 ldo2 output of ldo2 connect with a 1f capacitor to agnd 15 ldo1 output of ldo1 connect with a 1f capacitor to agnd 16 vout charge pump output all led anode pins should be connected to this pin requires a 2.2f capacitor to pgnd 17 c2+ positive connection to bucket capacitor 2 requires a 1f capacitor connected to c2- 18 c1+ positive connection to bucket capacitor 1 requires a 1f capacitor connected to c1- 19 vin battery voltage input connect with a 1f capacitor to pgnd 20 c1- negative connection to bucket capacitor 1 requires a 1f capacitor connected to c1+ t thermal pad thermal pad for heatsinking purposes connect to ground plane using multiple vias not connected internally
SC624 11 block diagram oscillator current setting dac semwire tm digital interface and logic control mahxlife tm fractional charge pump (1x, 1.5x, 2x) voltage setting dac ldo1 ldo2 vin vin 4 5 6 7 15 14 8 9 2 12 10 18 11 20 17 1 c1+ c1- c2+ c2- vout 16 bl1 bl2 bl3 bl4 vin vin swif nc pgnd ldo2 ldo1 vout agnd bandgap reference 13 byp gref 19 nc 3nc
SC624 12 general description this design is optimized for handheld applications supplied from a single li-ion cell and includes the following key features: a high e ciency fractional charge pump that supplies power to all leds four matched current sinks that control led backlighting current, with 0.5ma to 25ma per led two adjustable ldos with outputs ranging from 2.5v to 3.3v for ldo1 and 1.5v to 1.8v for ldo2, adjustable in 100mv increments a semwire single wire interface that provides control of all device functions high current fractional charge pump the backlight outputs are supported by a high e ciency, high current fractional charge pump output at the vout pin. the charge pump multiplies the input voltage by 1, 1.5, or 2 times. the charge pump switches at a xed frequency of 250khz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve e ciency. the mode selection circuit automatically selects the 1x, 1.5x or 2x mode based on circuit conditions. circuit conditions such as low input voltage, high output current, or high led voltage place a higher demand on the charge pump output. a higher numerical mode may be needed momentarily to maintain regulation at the vout pin during intervals of high demand, such as the droop at the vin pin during a supply voltage transient. the charge pump responds to these momentary high demands, setting the charge pump to the optimum mode (1x, 1.5x or 2x), as needed to deliver the output voltage and load current while optimizing e ciency. hysteresis is provided to prevent mode toggling. the charge pump requires two bucket capacitors for low ripple operation. one capacitor must be connected ? ? ? ? between the c1+ and c1- pins and the other must be connected between the c2+ and c2- pins as shown in the typical application circuit diagram. these capacitors should be equal in value, with a minimum capacitance of 1f to support the charge pump current requirements. the device also requires a 1f capacitor on the vin pin and a 2.2f capacitor on the vout pin to minimize noise and support the output drive requirements. capacitors with x7r or x5r ceramic dielectric are strongly recommended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coe cients make them unsuitable for this application. led backlight current sinks the backlight current is set via the semwire interface. the current is regulated to one of 32 values between 0.5ma and 25ma. the step size varies depending upon the current setting. between 0.5ma and 12ma, the step size is 0.5ma. the step size increases to 1ma for settings between 12ma and 15ma and 2ma for settings greater than 15ma. this feature allows ner adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in led brightness. all backlight current sinks have matched currents, even when there is variation in the forward voltages (v f ) of the leds. a v f of 1.2v is supported when the input voltage is at 3.0v. higher v f led mis-match is supported when v in is higher than 3.0v. all current sink outputs are compared and the lowest output is used for setting the voltage regulation at the vout pin. this is done to ensure that su cient bias exists for all leds. the backlight leds default to the o state upon power- up. for backlight applications using less than four leds, any unused output must be left open and the unused led driver must remain disabled. when writing to the backlight enable control register, a zero (0) must be written to the corresponding bit of any unused output. applications information
SC624 13 applications information (continued) backlight quiescent current the quiescent current required to operate all four backlights is reduced by 1.5ma when backlight current is set to 4.0ma or less. this feature results in higher e ciency under light-load conditions. further reduction in quiescent current will result from using fewer than four leds. fade-in and fade-out backlight brightness can be set to automatically fade-in when current is set to increase and fade-out when current is set to decrease. when enabled with a new current setting, the current will step through each incremental setting between the old and new values. the result is a visually smooth change in brightness with a rate of fade that can be set to 8, 16, 24, or 32 ms per step. programmable ldo outputs two low dropout (ldo) regulators are provided for camera module i/o and core power. each ldo has at least 100ma of available load current with 3.5% accuracy. the minimum current limit is 200ma, so outputs greater than 100ma are possible at somewhat reduced accuracy. a 1f, low esr capacitor should be used as a bypass capacitor on each ldo output to reduce noise and ensure stability. in addition, it is recommended that a minimum 22nf capacitor be connected from the byp pin to ground to minimize noise and achieve optimum power supply rejection. a larger capacitor can be used for this function, but at the expense of increasing turn- on time. capacitors with x7r or x5r ceramic dielectric are strongly recommended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coe cients make them unsuitable for this application. shutdown state the device is disabled when the swif pin is low. all registers are reset to default condition when swif is low. sleep mode when all leds are o , sleep mode is activated. this is a reduced current mode that helps minimize overall current consumption by turning o the clock and the charge pump while continuing to monitor the serial interface for commands. both ldos can be powered up while in sleep mode. semwire single wire interface functions all device functions can be controlled via the semwire single wire interface. the interface is described in detail in the semwire interface section of the datasheet. protection features the SC624 provides several protection features to safeguard the device from catastrophic failures. these features include: output open circuit protection over-temperature protection charge pump output current limit ldo current limit led float detection output open circuit protection over-voltage protection (ovp) is provided at the vout pin to prevent the charge pump from producing an excessively high output voltage. in the event of an open circuit at vout, the charge pump runs in open loop and the voltage rises up to the ovp limit. ovp operation is hysteretic, meaning the charge pump will momentarily turn o until v out is su ciently reduced. the maximum ovp threshold is 6.0v, allowing the use of a ceramic output capacitor rated at 6.3v with no fear of over-voltage damage. over-temperature protection the over-temperature (ot) protection circuit helps prevent the device from overheating and experiencing a catastrophic failure. when the junction temperature exceeds 160 c, the device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. all register information is retained during thermal shutdown. ? ? ? ? ?
SC624 14 charge pump output current limit the device also limits the charge pump current at the vout pin (typically 300ma). ldo current limit the device limits the output currents of ldo1 and ldo2 to help prevent it from overheating and to protect the loads. the minimum limit is 200ma, so load current greater than the rated 100ma can be used with degraded accuracy and larger dropout without tripping the current limit. applications information (continued) led float detection float detect is a fault detection feature of the led current sink outputs. if an output is programmed to be enabled and an open circuit fault occurs at any current sink output, that output will be disabled to prevent a sustained output ovp condition from occurring due to the resulting open loop. float detect ensures device protection but does not ensure optimum performance. unused led outputs must be disabled to prevent an open circuit fault from occurring.
SC624 15 pcb layout considerations the layout diagram in figure 1 illustrates a proper two-layer pcb layout for the SC624 and supporting components. following fundament al layout rules is critical for achieving the performance speci ed in the electrical characteristics table. the following guidelines are recommended when developing a pcb layout: place all bypass and decoupling capacitors c1, c2, cin, cout, cldo1, cldo2, and cbyp as close to the device as possible. all charge pump current passes through vin, vout, and the bucket capacitor connection pins. ensure that all connections to these pins make use of wide traces so that the resistive drop on each connection is minimized. the thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer. ? ? ? applications information (continued) make all ground connections to a solid ground plane as shown in the example layout (figure 3). if a ground layer is not feasible, the following groupings should be connected: pgnd cin, cout agnd ground pad, cldo1, cldo2, cbyp if no ground plane is available, pgnd and agnd should be routed back to the negative battery terminal as separate signals using thick traces. joining the two ground returns at the terminal prevents large pulsed return currents from mixing with the low-noise return currents of the ldos. both ldo output traces should be made as wide as possible to minimize resistive losses. ? ? ? ? ? ? cout c1 c2 cin cbyp cldo2 bl1 bl2 bl4 ldo1 ldo2 byp c1- c2- vin c1+ c2+ vout swif agnd gref bl3 vin vout SC624 nc nc gnd cldo1 gnd pgnd nc figure 1 recommended pcb layout figure 2 layer 1 figure 3 layer 2
SC624 16 register map address d7 d6 d5 d4 d3 d2 d1 d0 reset value description 0x00 fade_1 fade_0 fade_en bl_4 bl_3 bl_2 bl_1 bl_0 0x00 backlight current control 0x01 0 (1) 0 (1) 0 (1) 0 (1) blen_4 blen_3 blen_2 blen_1 0x00 backlight enable control 0x03 0 (1) ldo2_2 ldo2_1 ldo2_0 ldo1_3 ldo1_2 ldo1_1 ldo1_0 0x00 ldo control notes: (1) 0 = always write a 0 to these bits register and bit de nitions backlight current control register (0x00) this register is used to set the currents for the backlight current sinks, as well as to enable and set the fade step rate. these current sinks need to be enabled in the backlight enable control register to be active. fade[1:0] these bits are used to set the rise/fall rate between two backlight currents as follows: fade_1 fade_0 fade feature rise/fall rate (ms/step) 0 0 32 01 24 10 16 11 8 the number of steps in changing the backlight current will be equal to the change in binary count of bits bl[4:0]. fade_en this bit is used to enable or disable the fade feature. when the fade function is enabled and a new backlight current is set, the backlight current will change from its current value to a new value set by bits bl[4:0] at a rate of 8ms to 32ms per step. a new backlight level cannot be written during an ongoing fade operation, but an ongoing fade operation may be cancelled by resetting the fade bit. clearing the fade bit during an ongoing fade operation changes the backlight current immediately to the value of bl[4:0]. the number of counts to complete a fade operation equals the di erence between the old and new backlight values to increment or decrement the bl[4:0] bits. if the fade bit is cleared, the current level will change immediately without the fade delay. the rate of fade may be changed dynamically, even while a fade operation is active, by writing new values to the fade_1 and fade_0 bits. the total fade time is determined by the number of steps between old and new backlight values, multiplied by the rate of fade in ms/step. the longest elapsed time for a full scale fade-out of the backlight is nominally 1.024 seconds when the default interval of 32ms is used.
SC624 17 register and bit de nitions (continued) bl[4:0] these bits are used to set the current for the backlight current sinks. all enabled backlight current sinks will sink the same current, as shown in table 1. bl_4 bl_3 bl_2 bl_1 bl_0 backlight current (ma) 00000 0.5 00001 1.0 00010 1.5 00011 2.0 00100 2.5 00101 3.0 00110 3.5 00111 4.0 01000 4.5 01001 5 01010 5.5 01011 6 01100 6.5 01101 7 01110 7.5 01111 8 10000 8.5 10001 9 10010 9.5 10011 10 10100 10.5 10101 11 10110 11.5 10111 12 11000 13 11001 14 11010 15 11011 17 11100 19 11101 21 11110 23 11111 25 table 1 backlight current control bits bl enable control register (0x01) this register is used to enable the backlight current sinks. blen[4:1] these bits are used to enable current sinks (active high, default low). blen_4 enable bit for backlight bl4 blen_3 enable bit for backlight bl3 blen_2 enable bit for backlight bl2 blen_1 enable bit for backlight bl1 when enabled, the current sinks will carry the current set by the backlight current control bits bl[4:0], as shown in table 1.
SC624 18 ldo control register (0x03) this register is used to enable the ldos and to set their output voltages. ldo2[2:0] these bits are used to set the output voltage of ldo2, as shown in table 2. ldo2_2 ldo2_1 ldo2_0 ldo2 output voltage 0 0 0 off 0 0 1 1.8v 0 1 0 1.7v 0 1 1 1.6v 1 0 0 1.5v 101 through 111 are not used off table 2 ldo2 control bits ldo1[3:0] these bits set the output voltage of ldo1, as shown in table 3. ldo1_3 ldo1_2 ldo1_1 ldo1_0 ldo1 output voltage 0000off 0001 3.3v 0010 3.2v 0011 3.1v 0100 3.0v 0101 2.9v 0110 2.8v 0111 2.7v 1000 2.6v 1001 2.5v 1010 through 1111 are not used off table 3 ldo1 control bits register and bit de nitions (continued)
SC624 19 semwire interface functions the swif pin is a write-only single wire interface. it provides the capability to address up to 32 registers to control device functionality. the protocol for using this interface is described in the following subsections. driving the swif pin the swif pin should be driven by a gpio from the system microcontroller. the output level can be con gured as either a push-pull driver (ttl or cmos levels) or as an open drain driver with an external pull-up resistor. enabling the device the swif pin must be pulled from low to high for a period of greater than 1ms (t en ) to enable the device into the sleep state. in the sleep state, the device bandgap is active, uvlo monitoring is active, and the serial interface is monitored for communication. automatic sleep state if the backlight current sinks are disabled, the device automatically enters the sleep state in order to minimize the current draw from the battery. when in sleep mode, the charge pump and oscillator are both disabled. the ldos remain on if enabled. disabling the device the swif pin must be pulled from high to low for a period greater than 10ms (t dis ) in order to shut down the device. in this state the device remains disabled until the swif pin is pulled high for a period greater than 1ms. all registers return to the default state. semwire communication protocol and timing the following six step communication sequence controls all device functions when the device is enabled. osc on the swif pin is toggled low for one bit duration and high for one bit duration in order to enable the oscillator. the oscillator is turned o in the sleep state to minimize quiescent current. sample the swif pin is toggled low for one bit duration and high for one bit duration. during this time, the device samples the bit rate and determines the bit rate at which the register address and data values that follow will arrive. the sample rate is at least 20 times the bit rate ensuring robust communication synchronization. start the swif pin is pulled low for one bit duration, which starts communication with the target register. address the next 5 bits are the address of the target register msb rst, lsb last. data the next 8 bits are the data written to the target register msb rst, lsb last. standby after the last data bit is sent, the swif pin is pulled high for 5 bit durations to return the device to standby before another data write can take place. if all leds are disabled, the device will go back to sleep mode. note: the bit rate must be set by the host controller to a rate that is between the minimum and maximum frequencies listed in the electrical characteristics section. 1. 2. 3. 4. 5. 6. semwire interface
SC624 20 semwire interface (continued) single write operation device disabled device enabled into sleep resume sleep if all leds are off device disabled when low for t dis start a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t > t en data sample osc on register address t > d dl t > t dis 5 high bits min. concatenated write operation start a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 start t > d dl sample osc on (repeated) osc on sample register address data to concatenate write operations, repeat osc on, sample and start after the do bit of the previous sequence as shown.
SC624 21 e 1 2 n pin 1 indicator (laser mark) a1 a a2 c seating plane e/2 d/2 b .006 .008 .010 0.15 0.20 0.25 lxn bxn d1 e1 coplanarity applies to the exposed pad as well as the terminals . 2. controlling dimensions are in millimeters (angles in degrees). 1. inches dimensions nom e bbb aaa a1 a2 d1 e1 dim n l e min d a millimeters max min max nom e b d .114 .118 3.00 .122 2.90 3.10 notes: bbb c a b aaa c .003 .061 20 .067 .000 .020 - - (.006) 0.08 20 .071 1.55 .024 .002 0.00 0.50 1.80 1.70 0.05 0.60 (0.1524) - - .004 0.10 1.55 2.90 1.70 1.80 3.00 3.10 0.40 bsc .016 bsc 0.30 .012 .020 .016 0.40 0.50 .122 .118 .114 .071 .067 .061 a dap is 1.90 x 190mm. 3. outline drawing mlpq-ut-20 3x3
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC624 22 land pattern mlpq-ut-20 3x3 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. c z r y x g p h .146 .004 .008 .031 .083 .067 .016 3.70 0.20 0.80 0.10 1.70 0.40 2.10 dim (2.90) millimeters dimensions (.114) inches controlling dimensions are in mi llimeters (angles in degrees). 2. k .067 1.70 thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. failure to do so may compromise the thermal and/or 3. h k r (c) x p y g z

▲Up To Search▲

Price & Availability of SC624

	To Download SC624 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .